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ds05-20884-2e fujitsu semiconductor data sheet flash memory cmos 32m (4m 8) bit nand-type mbm30lv0032 n n n n description the mbm30lv0032 device is a single 3.3 v 4m 8 bit nand flash memory organized as 528 byte 16 pages 512 blocks. each 528 byte page contains 16 bytes of optionally selected spare area which may be used to store ecc code(specifications indicated are on condition that ecc system would be combined.). program and read data is transferred between the memory array and page register in 528 byte increments. a 528 byte page can be programmed in 200 m s and an 8k byte block can be erased in 2 ms under typical conditions. an internal controller automates all program and erase operations including the verification of data margins. data within a page can be read with a 50 ns cycle time per byte. the i/o pins are utilized for both address and data input/output as well as command inputs. the mbm30lv0032 is an ideal solution for applications requiring mass non-volatile storage such as solid state file storage, digital recording, image file memory for still cameras, and other uses which require high density and non-volatile storage. n n n n product line up n n n n packages part no. mbm30lv0032 operating temperature C40c to +85c v cc +2.7 v to +3.6 v power dissipation (max.) read 72 mw erase / program 72 mw ttl standby 3.6 mw cmos standby 0.18 mw marking side marking side (fpt-44p-m07) (normal bend) (fpt-44p-m08) (reverse bend) 44-pin plastic tsop (ii)
mbm30lv0032 2 n n n n features ? 3.3 v-only operating voltage (2.7 v to 3.6 v) minimizes system level power requirements ? organization memory cell array : (4m + 128k) 8 bit data register : (512 + 16) 8 bit ? automatic program and erase page program : (512 + 16) byte block erase : (8k + 256) byte ? 528 byte page read operation random access : 7 m s (max.) serial access : 35 ns (max.) ? fast program and erase program time : 200 m s (typ.) / page block erase time : 2 ms (typ.) / block ? command/address/data multiplexed i/o port ? hardware data protection ? 1,000,000 write/erase cycle guaranteed (ecc system required) ? command register operation ? package 44(40)-pin tsop type ii (0.8 mm pitch) normal/reverse type ? data retention: 10 years
mbm30lv0032 3 n n n n pin assignments vss cle ale we wp n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. i/o0 i/o1 i/o2 i/o3 vss vcc ce re r/b se n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. i/o7 i/o6 i/o5 i/o4 vccq vss cle ale we wp n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. i/o0 i/o1 i/o2 i/o3 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 fpt-44p-m07 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 fpt-44p-m08 top view vcc ce re r/b se n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. i/o7 i/o6 i/o5 i/o4 vccq n.c. n.c.
mbm30lv0032 4 n n n n pin descriotions pin number pin name descriptions 18 to 21 24 to 27 i/o0 to i/o7 data input/output the i/o ports are used for transferring command, address, and input/output data into and out of the device. the i/o pins will be high impedance when the outputs are disabled or the device is not selected. 2cle command latch enable the cle signal enables the acquisition of the made command into the internal com- mand register. when cle=h, command are latched into the command register from the i/o port upon the rising edge of the we signal. 3ale address latch enable the ale signal enables the acquisition of either address or data into the internal ad- dress/data register. the rising edge of we latch in addresses when ale is high and data when ale is low. 43 ce chip enable the ce signal is used to select the device. when ce is high, the device enters a low power standby mode. if ce transitions high during a read operation, the standby mode will be entered. however, the ce signal is ignored if the device is in a busy state(r/b =l) during a program or erase operation. 42 re read enable the re signal controls the serial data output. the falling edge of re drives the data onto the i/o bus and increments the column address counter by one. 4we write enable the we signal controls writes from the i/o port. data, address, and commands on the i/o port are latched upon the rising of the we pulse. 5wp write protect the wp signal protects the device against accidental erasure or programming dur- ing power up/down by disabling the internal high voltage generators. wp should be kept low when the device powers up until v cc is above 2.5 v. during power down, wp should be low when v cc falls below 2.5 v. 40 se spare area enable the se input enables the spare area during sequential data input, page program, and read 1. 41 r/b ready busy output the r/b output signal is used to indicate the operating status of the device. during program, erase, or read, r/b is low and will return high upon the completion of the operation. the output buffer for this signal is an open drain. 23 v cc q output buffer power supply the vccq input supplies the power to the i/o interface logic. this power line is elec- trically isolated from v cc for the purpose of supporting 5v tolerant i/o. 44 v cc power supply 1,22 v ss ground 6 to 17 28 to 39 n.c. no connection
mbm30lv0032 5 n n n n block diagram ce ale cle se wp re we v cc v ss i/o0 to i/o7 r/b x decoder v cc q state machine high voltage pumps i/o register & buffer command register status register y-decoder y-decoder memory array data register & s/a data register & s/a address register
mbm30lv0032 6 n n n n schematic cell layout and address assignment the program operation is implemented in page units while the erase operation is carried out in block units. a 0 to a 7 : column address a 9 to a 21 : page address (a 8 is automatically set to low or high by the 00h command or the 01h command in device inside.) * : x = v ih or v il table 1 addressing i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 first cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 second cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 third cycle a 17 a 18 a 19 a 20 a 21 x* x* x* 16 512 i/o0 i/o7 16 pages ? 1 block 8 i/o 528 8192 pages (512 blocks) memory cell array register 1) a page consists of (512+16) bytes; - 512 bytes for main memory - 16 bytes for redundancy or other use 2) a block consists of 16 pages; (8k+256) bytes. 3) total device density = read and program operation are executed through register register = 1 page size 528 bytes 16 pages 512 blocks. figure 1 schematic cell layout a 13 to a 21 : block address a 9 to a 12 : page address in block
mbm30lv0032 7 n n n n device bus operations *1: h: v ih , l: v il , x: v ih or v il *2: wp should be biased to cmos high or cmos low for standby. *3: when se is high, spare area is deselected. *4: if 50h command is input and read/program operation is executed only for spare area, se must be low at the command/address input. *: h: v ih , l: v il , x: v ih or v il table 2 operation table *1 mode cle ale ce we re se wp read mode command input h l l h x *4 x address input (3 clock) l h l h x *4 x during read (busy) l l l h h l/h *3 x sequential read & data output l l l h l/h *3 x program/ erase mode command input h l l h x *4 h address input (2 or 3 clock) l h l h x *4 h data input l l l h l/h *3 h during program (busy) xxxxx l/h *3 h during erase (busy) xxxxxx h write protect xxxxxx l stand-by x x h x x 0 v/v cc *2 0 v/v cc *2 table 3 read mode operation status * operation cle ale ce we re i/o0 to i/o7 power output select l l l h l data output active output deselect l l l h h high impedance active standby x x h x x high impedance standby
mbm30lv0032 8 n n n n command operation *1: the 00h command defines starting address on the 1st half page. *2: the 01h command defines starting address on the 2nd half page. *3: the 50h command is valid only when se is low level. table 4 command table function 1st cycle 2nd cycle acceptable command during busy state read (1) 00h *1 read (2) 01h *2 read (3) 50h *3 sequential data input 80h page program 10h block erase 60h d0h reset ffh status read 70h id read 90h
mbm30lv0032 9 n n n n functional description read mode there are three distinct commands used for the read operation: 00h, 01h, and 50h. after the command cycle, three address cycles are used to input the starting address. upon the rising edge of the final we pulse, there is a 7 m s latency in which the 528 byte page is transferred to the data register. the r/b signal may be used to monitor the completion of the data transfer. in the read operation, the ce signal must stay low after the third address input and during busy state. if the ce signal goes high during this period, the read operation will be terminated and then the standby mode will be entered. once the page of data has been loaded into the data register, it may be clocked out with consecutive 50 ns re pulses. each re pulse will automatically advance the column address by one. once the last column has been read, the page address will automatically increment by one and the data register will be updated with the new page after 7 m s. the 00h read command will set the pointer to the first half page of the array while the 01h read command will set it in the second half. it may be logical to think of 00h as a command which sets a 8 = 0 while 01h sets a 8 = 1. the 50h command set the pointer to the spare area, consisting of columns 512 to 527. during this read mode, a 3 to a 0 is used to set the starting address of the spare area. as with the 00h and 01h operations, once the spare area page is loaded into the data register, it may be read out by re pulses. each re pulse will increment the column address until the final column (527) is reached. at this time, the pointer will be reset to column 512 while the page address is incriminated and the data register is updated. the 00h or 01h command is required to move the pointer back into the main array area. read (1), (2): 00h/01h the read (1), (2) mode is invoked by latching the 00h or 01h command into the command register. this mode (00h) will be automatically selected when the device powers up. cle ce we ale re i/o0 to i/o7 y x x r/b 00h data output starting address command 01h 0 255 511 527 (column address) page (row) address x yy figure 2 read mode (1), (2) operation
mbm30lv0032 10 read (3): 50h the read (3) mode has identical timing to that of read (1) and (2). however, while read (1) and (2) are used to access the array, read (3) is used to access the 16 byte spare area. when the 50h command is executed, the pointer will be set to an address space between columns 512 and 527. the values of y will complete the address decoding. during this operation, only address bits a 3 to a 0 are used to determine the starting column address; a 7 to a 4 are ignored. a 21 to a 9 are used to determine the starting row address. sequential read each re pulse used to output data from the data register will cause the column address pointer to increment by one. when the final column has been reached, the next page will be automatically loaded into the data register. the r/b signal may be used to monitor the completion of the data transfer. cle ce we ale re i/o0 to i/o7 y x x r/b 50h data output starting address command 0 255 511 527 (column address) page (row) address x y figure 3 read mode (3) operation 0 i/o0 to i/o7 r/b address input data data data 00h/01h/50h 0 255 511 527 50h, se=l 0 255 511 527 00h, se=h 0 255 511 527 01h, se=l 0 255 511 527 00h, se=l figure 4 sequential read
mbm30lv0032 11 page program: 80h, 10h the device is programmed either by the page or partial page. programming is done by issuing the 80h command followed by three address cycles then serial data input. the 80h command may be preceded by either 00h, 01h or 50h to set the pointer to either the first half page, second half page, or spare area respectively. if the pointer command is not specifically issued, its location is determined by its previous use (see application note (2) ). after the serial data input, any column address which did not receive new data will not be programmed. this enables a page to be partially programmed. after the data has been entered, the 10h command will initiate the embedded programming process. if the 10h command is issued without loading any new data, programming will not be initiated. a given page may not be partially programmed more than ten consecutive times without an intervening erase operation. during the programming cycle, the r/b pin or status register bit i/o6 may be used to monitor the completion of the programming cycle. only the reset and read status commands are valid while programming is in progress. after programming, the status register bit i/o0 should be checked to verify whether the procedure was successful or not. block erase: 60h the device data is erased in a block consisting of sixteen pages. the erase operation begins with the 60h command followed by two address cycles in which the block to be erased is entered. while the two address cycles require a 21 to a 9 to be entered, a 12 to a 9 are dont care bits. once the block address is successfully loaded, the d0h command is entered to initiate the erase operation. the r/b signal may be used to monitor the completion of the cycle. upon completion, the status register bit i/o0 should be used to verify a successful erase. 10h 70h i/o0 address and data input 80h i/o0 to i/o7 r/b 0 = pass 1 = fail figure 5 page program d0h 70h i/o0 address input 60h i/o0 to i/o7 r/b 0 = pass 1 = fail figure 6 block erase
mbm30lv0032 12 read id: 90h this mode allows the identification of the manufacturer and product. after the 90h command cycle, one address cycle follows in which 00h is entered. the next two re pulses will output the manufacturer and device code respectively. status read: 70h the status register may be used to determine if the device is ready, in the write protect mode, or passed program/erase operations. after the 70h command is entered, the more recent falling edge of either ce or re will output the contents of the status register to i/o0 to 7. the status register is continually updated and does not require either ce or re to be toggled. by utilizing the ce pin, multiple devices with r/b pins wired together may be polled to determine their specific status. table 5 code table i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 code manufacturer 00000100 04h device 11100011e3h table 6 status output table status description i/o0 program/erase 0 = pass; 1 = fail i/o1 not used i/o2 not used i/o3 not used i/o4 not used i/o5 not used i/o6 ready/busy 0 = busy; 1 = ready i/o7 write protect 0 = protected; 1 = unprotected e3h 04h 90h 00h re i/o0 to i/o7 manufacturer code device code figure 7 read id operation
mbm30lv0032 13 reset when the device is busy during program, erase, or read, it can be reset by entering the command ffh. if wp = 1, the status register will be set to c0h. if a reset command is issued while the device is in the reset state, the command will be ignored. if the device is reset during the program or erase operations, the internal high voltages will be discharged before r/b goes high. device(1) ce(1) device(2) ce(2) device(n) ce(n) 0/1 0/1 ale cle we re 8 i/o0 to i/o7 r/b r/b ale cle we ce(1) ce(n) re i/o0 to i/o7 status of device(1) status of device(n) 70h 70h figure 8 status read ffh r/b i/o0 to i/o7
mbm30lv0032 14 n n n n absolute maximum ratings *: minimum dc voltage on input or i/o pins is - 0.5v. during voltage transitions, inputs may undershoot vss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input pins is v cc + 0.5 v and on i/o pins are v cc q + 0.5 v. during voltage transitions,input pins may overshoot to v cc + 2.0 v for periods of up to 20ns and i/o pins may overshoot to v cc q + 2.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions *: v cc q = 5.0 v 10 % can be guaranteed on v cc 3 3.0 v. note: operating ranges define those limits between which the functionality of the device is quaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. ambient temperature with power applied t a C40 +85 c storage temperature tstg C55 +125 c voltage on a i/o pin with respect to ground * v i/o C0.6 v cc q +0.5 v voltage on a pin except i/o with respect to ground * v in C0.6 v cc +0.5 v power supply voltage v cc C0.6 +5.5 v v cc q C0.6 +6.0 parameter symbol value unit min. max. supply voltages v cc +2.7 +3.6 v supply voltages v cc q * +2.7 +5.5 v voltages v ss 0 v ambient temperature t a C40 +85 c
mbm30lv0032 15 n n n n electrical characteristics 1. dc characteristics parameter symbol conditions value unit min. typ. max. sequential read current i cc1 t cycle = 50 ns, ce = v il , i out = 0 ma 1020ma command address input current i cc3 t cycle = 50 ns, ce = v il 1020ma data input current i cc4 10 20 ma program current i cc6 10 20 ma erase current i cc7 10 20 ma stand-by current (ttl) i sb1 ce = v ih , wp = se = 0 v/v cc 1ma stand-by current (cmos) i sb2 ce = v cc C0.2 v, wp = se = 0 v/ v cc 1050a input leakage current i li v in = 0 to 3.6 v 10 a output leakage current i lo v out = 0 to 3.6 v 10 a input high voltage v ih i/o pins 2.0 v cc q +0.3 v except i/o pins 2.0 v cc +0.3 v input low voltage v il C0.3 0.8 v output high voltage level v oh i oh = C400 m a2.4v output low voltage level v ol i ol = 2.1 ma 0.4 v output low current (r/b )i ol v ol = 0.4 v 8 10 ma
mbm30lv0032 16 2. ac characteristics (note 1) (continued) parameter symbol value unit min. max. cle setup time t cls 0ns cle hold time t clh 10 ns ce setup time t cs 0ns ce hold time t ch 10 ns write pulse width t wp 25 ns ale setup time t als 0ns ale hold time t alh 10 ns data setup time t ds 20 ns data hold time t dh 10 ns write cycle time t wc 50 ns we high hold time t wh 15 ns wp high to we low t ww 100 ns ready to re falling edge t rr 20 ns read pulse width t rp 30 ns read cycle time t rc 50 ns re access time (serial data access) t rea 35ns ce high time for the last address in serial read cycle (note 3) t ceh 100 ns re access time (id read) t reaid 35ns re high to output high impedance t rhz 15 30 ns ce high to output high impedance t chz 20ns re high hold time t reh 15 ns output high impedance to re falling edge t ir 0ns re access time (status read) t rsto 35ns ce access time (status read) t csto 45ns we high to re low t whr 60 ns ale low to re low (id read) t ar1 100 ns ce low to re low (id read) t cr 100 ns data transfer from memory cell array to register t r 7 m s we high to busy t wb 100 ns
mbm30lv0032 17 (continued) notes: 1. ac test conditions: 2. the time to go from ce high to ready depends on the pull-up resister of the r/b pin (see application notes (6)) toward the end of this document. 3. in case that toggling ce to high after access to the last address (address 527) in the resister in the read mode (1), (2), and (3), the ce high time must be held for 100 ns or more when the delay time of ce with respect to re is 0 to 200 ns (see the figure below). when the ce delay time is within 30 ns, the device is kept in the ready state and will output no busy signal. parameter symbol value unit min. max. ale low to re low (read cycle) t ar2 50 ns re last clock rising edge to busy (in sequential read) t rb 100ns ce high to ready (in case of interception by ce in read mode) (note 2) t cry 50 + tr (r/b ) ns device resetting time (read/program/erase) t rst 5/10/500 m s operating range v cc = 2.7 to 3.6 v v cc = 3.0 to 3.6 v input level 2.4 v/0.4 v input comparison level 1.5 v/1.5 v output data comparison level 1.5 v/1.5 v output load 1ttl load capacitance (c l ) 50 pf 100 pf transition time (t t )5 ns t ceh 3 100 ns *v ih or v il a 527 511 526 510 525 509 busy a : 0 to 30 ns ? busy signal is not output. * ce re r/b
mbm30lv0032 18 n n n n erase and programming performance *1: refer to application note (10) toward the end of this document. *2: refer to application note (13) toward the end of this document. this specification is on conditions that ecc system would be combined. n n n n valid blocks the mbm30lv0032 occasionally contains unusable blocks. refer to application note (12) toward the end of this document. n n n n pin capacitance notes: 1. test conditions t a = 25 c, f = 1.0 mhz 2. sampled, not 100% tested. parameter symbol value unit remarks min. typ. max. average programming time t prog 200 1000 m s number of programming cycles on same page n 10 *1 block erasing time t berase 210ms number of program/erase cycles p/e 1 10 6 *2 parameter symbol value unit min. typ. max. valid block number n vb 502 ? 512 block parameter symbol condition value unit typ. max. input capacitance c in v in = 0 10 pf output capacitance c out v out = 0 10 pf
mbm30lv0032 19 n n n n timing diagrams cle ce we ale i/o0 to i/o7 t cls t cs t clh t ch t wp t als t alh t dh t ds : v ih or v il figure 9 command input cycle timing diagram t cls a 0 to a 7 a 9 to a 16 a 17 to a 21 t cs t wc t wc t wp t wh t wp t wh t wp t als t alh t ds t dh t ds t dh t ds t dh cle ce we ale i/o0 to i/o7 : v ih or v il figure 10 address input cycle timing diagram
mbm30lv0032 20 figure 11 data input cycle timing diagram d in n d in n+1 cle ce we i/o0 to i/o7 ale t clh t ch t als t wc t wp t wh t wp t wp t ds t dh t ds t dh d in * t ds t dh * : se = gnd input : to d in 527 = v cc input : to d in 511 : v ih or v il
mbm30lv0032 21 t rc ce re i/o0 to i/o7 r/b t rp t reh t rea t rea t rea t rhz t rhz t rhz t chz t rr t rp t rp figure 12 serial read cycle timing diagram 70h ce re i/o0 to i/o7 r/b cle we t cls t cls t cs t clh t wp t ch t csto t whr t chz t rhz t ds t dh status output t rsto t ir : v ih or v il figure 13 status read cycle timing diagram
mbm30lv0032 22 d out i/o0 to i/o7 cle ale t ceh t cry ** t rb 00h a 0 to a 7 a 9 to a 16 d out d out n + 1 n ce re r/b we t cls t cs t ch t clh t wc t als t alh t alh t r t ar2 t wb t rr t rc t ds t dh t ds t dh t ds t dh t ds t dh t rea column address n **:se = gnd input : d out 527 = v cc input : d out 511 : v ih or v il d out n + 2 a 17 to a 21 figure 14 read cycle (1) timing diagram note: the ce signal must stay low after the third address input and during busy state. 00h a 17 to a 21 a 9 to a 16 a 0 to a 7 d out n d out n + 1 d out n + 2 ce re r/b we t cls t cs t ch t clh t wc t als t alh t alh t r t ar2 t wb t rr t rc t ds t dh t ds t dh t ds t dh t ds t dh t rea t chz t rhz i/o0 to i/o7 column address n *** ***:read operation using 00h command read operation using 01h command n : 0 to 255 n : 256 to 511 cle ale : v ih or v il figure 15 read cycle (1) timing diagram: interrupted by ce note: the ce signal must stay low after the third address input and during busy state.
mbm30lv0032 23 01h d out d out d out t cls t clh t cs t ch t als t alh t ds t dh t ds t dh a 17 to a 21 a 9 to a 16 a 0 to a 7 t alh t wb t r t ar2 t rc t rr t rea 256 + m 256 + m + 1 **: se = gnd input : d out 527 = v cc input : d out 511 column address m ** cle ce we ale i/o0 to i/o7 r/b re : v ih or v il figure 16 read cycle (2) timing diagram note: the ce signal must stay low after the third address input and during busy state. figure 17 read cycle (3) timing diagram note: the ce signal must stay low after the third address input and during busy state. 50h d out d out d out t cls t clh t cs t ch t als t alh t ds t dh t ds t dh a 17 to a 21 a 9 to a 16 a 0 to a 7 t alh t wb t r t ar2 t rc t rr t rea 512 + m 512 + m + 1 **: se = gnd input : d out 527 = do not input v cc column address m ** cle ce we ale i/o0 to i/o7 r/b re : v ih or v il 527
mbm30lv0032 24 00h n+1 0 1 2 cle ce we ale i/o0 to i/o7 r/b re ** n+2 n ** t r t r column address n page address m page m access **: se = gnd input : d out 527 = v cc input : d out 511 : v ih or v il a 0 to a 7 a 9 to a 16 a 17 to a 21 figure 18 sequential read (1) timing diagram note: the ce signal must stay low after the third address input and during busy state. = v cc input : d out 511 01h 0 1 2 cle ce we ale i/o0 to i/o7 r/b re ** ** t r t r page m access **: se = gnd input : d out 527 page m + 1 access 256 + n 256 + n + 1 256 + n + 2 : v ih or v il a 0 to a 7 a 9 to a 16 a 17 to a 21 column address n page address m note: the ce signal must stay low after the third address input and during busy state. figure 19 sequential read (2) timing diagram
mbm30lv0032 25 50h a 0 to a 7 cle ce we ale i/o0 to i/o7 r/b re ** ** t r t r page m access page m + 1 access 512 513 514 : v ih or v il 512 + n 512 + n + 1 512 + n + 2 column address n page address m = do not input v cc **: se = gnd input : d out 527 a 9 to a 16 a 17 to a 21 figure 20 sequential read cycle (3) timing diagram note: the ce signal must stay low after the third address input and during busy state.
mbm30lv0032 26 t als 80h 10h 70h cle ce we ale r/b re t cls t cls t cs t cs t cls t ch t alh t als t ds t dh a 17 to a 21 a 9 to a 16 a 0 to a 7 d in * d in n+1 d in n status output t alh t prog t wb t ds t dh t dh t ds t ds t dh i/o0 to i/o7 : v ih or v il = v cc input : to d in 511 *: se = gnd input : to d in 527 figure 21 auto program operation timing diagram 60h d0h cle ce we ale r/b re i/o0 to i/o7 t cls t cs t clh t cls t als t alh t wb t berase t dh t ds a 9 to a 16 a 17 to a 21 status output auto block erase setup command erase start command status read command 70h : v ih or v il figure 22 auto block erase timing diagram
mbm30lv0032 27 90h 00h 04h e3h cle ce we ale re i/o0 to i/o7 t cls t cs t cls t cs t alh t cr t ar1 t ch t als t alh t ds t dh t reaid t reaid address input maker code device code t ch : v ih or v il figure 23 id read operation timing diagram
mbm30lv0032 28 n n n n application notes and comments (1) prohibition of unspecified commands the operation commands are listed in table 4. data input as a command other than the specified commands in table 4 is prohibited. stored data may be corrupted if an unspecified command is entered during the command cycle. (2) pointer action for program operation the pointer action can be done for program operation as follows. start only 50h area program? start address is in 00h area? input 01h command input 00h command *2 program sequence continue to program? the pointer is 01h? start address area (00h,01h,50h) is the same as the previous? program sequence start address area is changed from 01h to 00h? set 01h command input read command *3 continue to program? end input 50h command *1 yes no yes no no yes yes no no yes yes no yes no *1: if read operation was done setting start address in 50h area in previous use, the 50h command input can be skipped. *2: if read operation was done at 00h or (and) 01h area in previous use, the 00h command input can be skipped. *3: the read command means 00h, 01h or 50h. 0 255 511 527 00h 01h 50h figure 24 pointer action flow chart
mbm30lv0032 29 (3) acceptable commands after serial input command 80h when the serial input command (80h) is input for program execution, commands other than the program execution command (10h) or reset command (ffh) should not be input. if a command other than 10h or ffh is input, the program operation is not performed. (4) status read during the read operation when the status read command (70h) is input during reading, the next re clock signal can be input to read the value of the internal status register. since the internal operation mode is held in status read, read data will not be output even if the re clock signal is input after becoming ready. status read is therefore disabled at reading. when the read command (00h) is input during the period [a], the internal operation mode of the device can be canceled, making it possible to read data at address n without inputting add. (5) auto program failure 80 ff address input we r/b figure 25 reset command after 80h input 10 xx 80 other command programming will not be executed. in case of this operation, the ffh command is needed. 00 70 00 [a] n address status read command input status output status read we r/b ce re figure 26 status read during read operation if programming at page address (m) fails, data should be programmed at the page address (n) of another block. data input at first programming at page address (m) is lost. so address input using the 80h command must follow the same procedure as data input. 80 10 70 80 80 10 i/o 10 fail address m data input address n data input n m figure 27 auto program failure
mbm30lv0032 30 (6) r/b : termination of the ready/busy pin (r/b ) the r/b is open-drain output. when using the r/b , r/b must be pulled up v cc by a resistor. (7) power on/off sequence: after power-off, each input signal level may be undefined. use the wp signal as shown in the figure below. device v cc v cc r c l r/b v ss v cc (max.) e v ol i ol + i l 3.2 v 8 ma + i l r = = figure 28 termination for r/b 2.7 v 2.5 v v cc 0 v ce, we, re cle, ale wp don? care v il v ih operation don? care v il figure 29 power on/off sequence
mbm30lv0032 31 (8) setup for wp signal a low-level wp signal will force erasing and programming to be reset. to control, use the wp signal as shown below. we din wp r/b 80 10 t ww program 100 ns (min.) we din wp r/b 80 10 t ww program prohibition 100 ns (min.) we din wp r/b 60 d0 t ww erase 100 ns (min.) we din wp r/b 60 d0 t ww erase prohibition 100 ns (min.)
mbm30lv0032 32 (9) address input in 4 cycles the device will get addresses in three cycles. if addresses are input in four cycles, address input in the fourth cycle will be ignored in the chip. internal read operation starts when we in the third cycle goes high. read operation ignored cle ce we ale i/o0 to i/o7 r/b 00h, 01h or 50h address input figure 30 read operation when 4 address cycles are input program operation cle ce we ale i/o0 to i/o7 80h address input ignored data input figure 31 program operation when 4 address cycles are input
mbm30lv0032 33 (10) divided programming on same page the device uses the page programming method that allows programming up to ten times on the same page. the procedure for divided programming (programming on a part of one page) is shown below. (11) notification for re signal when the device is in the read mode, the re signal causes the internal column address counter to increment in synchronization with the re clock. if the 00h, 01h, or 50h command is input to the device in the read mode, the internal column address counter will count up even after the re signal is input prior to address input. at this mode, at input of the re signal beyond the last column address, the device will start reading (memory ? register) even without address input and may output the busy signal (sequential read is started). in this way, once the device enters the read mode, unintentional reading may be started after the re signal is input prior to addressing; therefore, the re signal should be input after address input. data pattern 1 column a column b page n the first programming data pattern 2 column c column d page n the second programming data pattern 3 column e column f page n the third programming ?o input or ? data pattern 1 column a column b page n result data pattern 2 column c column d data pattern 3 column e column f ?o input?or ? ?o input?or ? ?o input?or ? ?o input?or ? ? ? ? figure 32 divided program in the same page 00h/01h /50h i/o0 to i/o7 we address input re r/b figure 33 re input before address
mbm30lv0032 34 (12) invalid block (bad block) the device contains unusable blocks. therefore, the following issues must be recognized: (13) failure phenomena for program and erase operations repeated rewriting might cause an error at programming and erasing. possible error modes, and detection methods and remedies are listed in the following table. system-based remedies will provide a highly reliable system. * : (1) or (2) ecc : error correcting code ? hamming code etc. example : 1 bit correction & 2 bit detection. block replacement erase if an error occurs at erasing, like programming, remedies should be executed on a system basis to prevent access to blocks causing the error. failure mode detection and countermeasure sequence block erase failure status read after erase ? block replacement page program failure status read after prog. ? block replacement single bit* program failure 1 ? 0 (1) block verify after prog. ? retry (2) ecc bad block bad block valid (good) block number min. 502 typ. max. 512 unit block figure 36. shows the bad block test flow some mbm30lv0032 products have invalid blocks (bad blocks) at shipping. after mounting the device in the system, test whether there are no bad blocks. if there are any bad blocks, they should not be accessed. the bad blocks are connected to sense-amp of the bit lines via the selector transistors. good blocks will not be affected unless the bad blocks are accessed. the effective number of good blocks specified by fujitsu is shown below. figure 34 bad block program buffer memory error occurs block a block b if an error occurs in block a, reprogramming from the external buffer to block b. block a should not be accessed after an error occurs. figure 35 reprogramming to good block
mbm30lv0032 35 (14) ale input condition during address input the ale input must remain high once asserted until the last address byte has been written to the device. cle ce we ale i/o0 to i/o7 00h, 01h or 50h address input keep h inhibit l input read operation cle ce we ale i/o0 to i/o7 80h address input keep h inhibit l input program operation cle ce we ale i/o0 to i/o7 60h address input keep h inhibit l input d0h erase operation
mbm30lv0032 36 (15) inhibit re toggling during busy state the re input cannot be allowed to toggle during the period that a read data transfer operation is in process (busy state). if the re input toggles during that period, the internal column address will increment. (16) restriction on toggling the we the we input cannot be allowed to toggle past the end of page (byte 511 with se high or byte 527 with se low) during an input data operation. if the we input toggles past the end of page, the internal address counter will wrap around to the begging of the page and overwrite the information previously there. (17) reading past last device page when the last byte in the last page of the device is read, the internal address counter will wrap around to the fist page in the device. cle ce we ale re i/o0 to i/o7 r/b starting address y toggling x times ( ? inhibiting) start from column address y + x 80h 10h 70h cle ce we ale r/b re d in * d in output status i/o0 to i/o7 *: din for address 511 with se = "h" or 527 with se = "l" inhibit toggling : v ih or v il : invalid data
mbm30lv0032 37 (18) ce dont care timing for read and program operation ce can be dont-care (h or l) state during read and program operation as follows. a 17 to a 21 10h 80h d in 2 d in 1 d in 0 d in * a 9 to a 16 a 0 to a 7 d i/o0 to i/o7 command ce re we r/b t cs t ch t wp ce we t cea t rea d out ce re i/o0 to i/o7 ce we i/o0 to i/o7 (55 ns max.) : v ih or v il a 0 to a 7 a 9 to a 16 a 17 to a 21 d out n d out n+1 d out n+2 d out note: in the read operation, the ce signal must stay low after the third address input and during busy state. if the ce signal goes high during this period, the read operation will be terminated and then the standby mode will be entered.
mbm30lv0032 38 n n n n bad block test flow figure 36 bad block test flow test start page 1 & 2 blank check block no. = 0 test end set as a bad block yes no yes no b no. block no. = block no. + 1 ? all ffh? ? = 511 >
mbm30lv0032 39 n n n n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm30lv0032 -pftn device number/description mbm30lv0032 32 mega-bit (4m 8-bit) cmos flash memory 2.7 v to 3.6 v read, write, and erase package type pftn = 44-pin thin small outline package (tsop) standard pinout pftr = 44-pin thin small outline package (tsop) reverse pinout valid combinations mbm30lv0032 -pftn -pftr valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.
mbm30lv0032 40 n n n n package dimensions (continued) c 2000 fujitsu limited f44016s-1c-3 details of "a" part 0.30?.10 (.012?004) 18.41?.10 (.725?004) m 0.13(.005) 0.80(.0315)typ 16.80(.661)ref 0(0)min (stand off) .043 ?002 +.004 ?.05 +0.10 1.10 10.16?.10 (.400?004) 11.76?.20 (.463?008) 0.50?.10 (.020?004) 10.76?.20 (.424?008) 0.15?.05 (.006?002) 10 1 "a" index lead no. 0.15(.006)max 0.40(.016)max 0.15(.006) 0.25(.010) * 13 22 23 32 44 35 (mounting height) 0.10(.004) 44-pin plastic tsop (ii) (fpt-44p-m07) *: resin protrusion. (each side: 0.15(.006) max) dimensions in mm (inches)
mbm30lv0032 41 (continued) c 2 000 f uj it su limited f44 0 17 s -1 c - 3 details of "a" part 0.30?.10 (.012?004) 18.41?.10 (.725?004) m 0.13(.005) 0.80(.0315)typ 16.80(.661)ref 0(0)min (stand off) .043 ?002 +.004 ?.05 +0.10 1.10 10.16?.10 (.400?004) 11.76?.20 (.463?008) 0.50?.10 (.020?004) 10.76?.20 (.424?008) 0.15?.05 (.006?002) 10 1 "a" index lead no. 0.15(.006)max 0.40(.016)max 0.15(.006) 0.25(.010) * 13 22 23 32 44 35 (mounting height) 0.10(.004) dimensions in mm (inches) 44-pin plastic tsop (ii) (fpt-44p-m08) *: resin protrusion. (each side: 0.15(.006) max)
mbm30lv0032 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0012 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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